The present invention relates to a semiconductor device provided with semiconductor elements and to a method for the fabrication of such a semiconductor device. The present invention relates more particularly to a semiconductor device protecting its semiconductor elements and securing establishment of electrical connections between the semiconductor elements and external equipment.
In recent years, since electronic equipment is becoming smaller and smaller in size and being highly improved in function, there have been strong demands for improvement in packaging density as well as the miniaturization and the high operation rate of the semiconductor device. In order to meet these demands, various forms of packaging have been developed. For example, the COC (Chip On Chip) module has been developed as a packaging form (Japanese Unexamined Patent Gazette No. H10-32307).
Hereinafter, a semiconductor device of a conventional COC module (hereinafter referred to as the “COC”) and a method for the fabrication of such a COC will be described with reference to FIG. 5.
FIG. 5 schematically shows a cross section of the conventional COC 100. The COC 100 includes a first semiconductor chip 101 containing a first semiconductor integrated circuit part and a second semiconductor chip 102 containing a second semiconductor integrated circuit part. These first and second semiconductor chips 101 and 102 are electrically connected together by a face-down technique. Since the face-down technique is used, the major surface of the semiconductor chip 102 faces downward while the backside surface of the semiconductor chip 102 faces upward.
The first semiconductor chip 101 is mounted on a die pad 106a of a lead frame 106, and the second semiconductor chip 102, located above the first semiconductor chip 101, is smaller in chip size than the first semiconductor chip 101. Both the first semiconductor chip 101 and the second semiconductor chip 102 are encapsulated with an encapsulating resin 108.
Formed on the major surface of the first semiconductor chip 101 are a plurality of first element electrodes 103 electrically connected to the first semiconductor integrated circuit part. On the other hand, formed on the major surface of the second semiconductor chip 102 are a plurality of second element electrodes 104 electrically connected to the second semiconductor integrated circuit part. The first semiconductor chip 101 and the second semiconductor chip 102 are placed such that their major surfaces face each other, and a portion 103a of the first element electrodes 103 of the first semiconductor chip 101 and the second element electrodes 104 of the second semiconductor chip 102 are connected together electrically by a connection member (for example, a bump) 105. Further, a portion 103b of the first element electrodes 103 of the first semiconductor chip 101 is electrically connected to an external lead (an external electrode) 106b of the lead frame 106 by a boding wire (for example, a wire of Au).
Referring still to FIG. 5, a method for the fabrication of the conventional COC 100 will be described below.
First, the first semiconductor chip 101 and the second semiconductor chip 102 are prepared. Following this, the connection member 105, made of solder or the like, is formed on each of the second element electrodes 104 of the second semiconductor chip 102. Next, the second semiconductor chip 102 is mounted onto the first semiconductor chip 101 such that each of the second element electrodes 104 of the second semiconductor chip 102 is connected to each of the first element electrode portions 103a of the first semiconductor chip 101 through the connection member 105. Then, the connection member 105 is melted, thereby electrically connecting together the second element electrodes 104 of the second semiconductor chip 102 and the first element electrode portions 103a of the first semiconductor chip 101.
Next, the first semiconductor chip 101 is mounted onto the die pad 106a of the lead frame 106. This is followed by wire bonding of electrically connecting together the first element electrode portion 103b of the first semiconductor chip 101 and the external lead 106b of the lead frame 106 by a bonding wire (for example, a wire of Au). Lastly, the fist semiconductor chip 101, the second semiconductor chip 102, the die pad 106a of the lead frame 106, and a portion of the external lead 106b of the lead frame 106 are all encapsulated by the encapsulating resin 108, and the COC 100 is obtained.
However, the conventional COC 100 has difficulties in being multipin-ized to a further extent. That is, in the COC 100, external connection is established by the external lead 106b extracted from a lateral surface of the encapsulating resin (the package) 108, which makes it difficult to further provide many external electrodes (external terminals). Furthermore, the external dimensions of the COC 100 are constrained by the package dimensions such as the size of the lead frame 106. Therefore, it is difficult to reduce the size of the COC 100.
Bearing in mind the above-described problems, the present invention was made. Accordingly, a major object of the present invention is to provide a semiconductor device capable of coping with multipin-ization and reducible in size and a method for the fabrication of such a semiconductor device.